Castellated gate MOSFET tetrode capable of fully-depleted operation

ABSTRACT

A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of co-pending U.S. patentapplication Ser. No. 11/796,652, filed Apr. 27, 2007, to John J.Seliskar, entitled, “A Castellated Gate MOSFET Device Capable ofFully-Depleted Operation”, the contents of which are hereby expresslyincorporated herein by reference. Application Ser. No. 11/796,652 itselfis a continuation-in-part of parent application Ser. No. 10/940,093entitled “An Improved Fully-Depleted Castellated Gate MOSFET Device andMethod of Manufacture Thereof”, now U.S. Pat. Nos. 7,212,864 and7,439,139

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to field effect transistors(FET's) formed as complimentary metal oxide semiconductor (CMOS)structures and, more particularly, to new and improved MOSFET deviceshaving vertically oriented channel structures capable of fully depletedoperation. Specifically, the present invention relates to an improvedvertically oriented MOSFET device and method of fabrication thereofwhich incorporates a tetrode gate structure, thereby providing anintegrated cascode for high performance analog and mixed-signalapplications.

2. Description of the Prior Art

The progression of CMOS device scaling, that is planer MOSFET, has seena continuous shrinking of transistor dimensions in both the vertical andthe horizontal dimensions resulting in an approximate doubling of thenumber of transistors per unit area every 18 months or so. From theeconomics perspective, this scaling progression has resulted in CMOSbecoming the preeminent technology for packing system functions on atransistor chip. The desire to shrink gate channel lengths and hencearea, as width-to-length ratios remain roughly constant, requires thesimultaneous vertical scaling of both the gate oxide and thesource/drain junctions. This creates the requirement that the powersupply (Vdd) also scale, as indicated above. The power supply voltagemust scale so as to maintain gate oxide integrity (breakdown/wear-outdue to voltage stress), to provide adequate junction breakdown margin,and to minimize device lifetime reduction due to hot carrier injection.

While CMOS scaling has enabled the circuit and system designer to pack atremendous amount of functionality onto a silicon die, it hassimultaneously created a number of significant problems as far as thechip's ability to interface with the outside world. This is particularlytrue in the area of analog/digital mixed-signal chips, and in particularfor communication and power management applications which may be used orexist in a less-controlled signaling environment than found inall-digital systems. Some examples of the efforts to overcome this areillustrated in U.S. Pat. Nos. 4,393,391, 4,583,107, 5,675,164,5,801,417, 5,932,911, 6,111,296, 6,118,161, 6,207,511, 6,396,108, and6,413,802.

The continuing drive to utilize semiconductor chip area whilemaintaining I/O compatibility has resulted in the evolution of baselineCMOS ASIC/SOC process technologies that now have two gate oxides toaccount for the need to operate efficiently at two, and sometimes three,power supply levels. Having begun at roughly the 0.25 um node, this iscurrently the approach taken by certain mainstream ASIC/ASSPsemiconductor producers or foundries. These technology offeringsgenerally consist of a baseline process flow that has a fully scaled andoptimized thin oxide core device to the extent that the current processmanufacturing technology allows, and a thick oxide device which isessentially the core device from the previous technology generation.Unfortunately, in such technology evolution, the thick oxide I/O devicehas become somewhat of a “forgotten stepchild”, as only the thin-oxidecore devices can truly take advantage of the shrinking feature sizesthat are enabled by state-of-the-art photolithography. More importantly,as the thick oxide device is a “leftover” from the previous technologynode, it typically under-performs the thin-oxide core device in terms ofspeed/bandwidth (f_(t)).

The impact of this trend is particularly acute in the area of all-CMOSanalog and mixed analog/digital signal chips. These chips derive theiradvantage from the ability to integrate complex digital core functions,such as DSP, with analog signal processing functions, such asanalog-to-digital or digital-to-analog converters. While thisreliability-driven voltage trend results in lower power consumption fordigital functions, the effect is not necessarily the same in the analogcase. In fact, it has been shown that in an analog-to-digital converterapplication with a fixed dynamic range requirement, power consumptioncan actually increase with decreasing power supply.

At present, BiCMOS (bipolar-CMOS combination) technologies, andparticularly SiGe bipolar, offer a solution to some of the problemsdiscussed above. However, a number of difficulties persist including, inparticular, power consumption, cost and scalability. Bipolar devicesconsume significantly more power than CMOS devices, which increasespackage cost and at some point renders them unsuitable as a systemsolution, in particular for portable devices. From the standpoint ofscaling, bipolar technologies have hit an apparent limit in terms ofincreasing performance for a given density and power consumption. Theintegration of CMOS and bipolar devices (BiCMOS) reduces the powerconsumption problem but leads to a second difficulty, i.e. cost. Highperformance technologies, such as SiGe BiCMOS cost upwards of 25% ormore than CMOS devices at the same feature sizes. Finally, bipolardevices by nature, like the thick oxide CMOS I/O devices discussedearlier, cannot take full advantage of decreasing feature sizes whichresult from advances in wafer patterning technology (photolithography).

Clearly, the trends and problems discussed above may soon create asituation where it is no longer desirable to integrate a significantamount of analog functionality into a single-chip mixed-signal systemsolution, thus eliminating one of the traditional paths to reduce costand power consumption in electronic systems. Recently new devicestructures have been proposed to provide solutions which overcome theaforementioned problems, as is detailed in U.S. Pat. No. 7,212,864,mentioned in the cross-reference subsection of this application. Asshown in FIG. 1, the prior art castellated gate MOSFET triode device 3(or alternately, FDCG MOSFET) is a non-planar structure having lateralcurrent flow through a plurality of semiconductor channels. While theprior art device of U.S. Pat. No. 7,212,864 provides a number ofsolutions to the analog and mixed-signal problem in all-CMOStechnologies, some problems still exist in the quest to provide stillhigher performance and robustness.

One of the more persistent problems in the area of three terminalelectron devices, and field effect transistors in particular, is thewell known trade-off between device series resistance (R_(dsw)) andparasitic gate-to-drain, or source capacitance. Elements of this problemwere encountered early on during the era of the vacuum tube triode,leading to the development of the vacuum tube tetrode (British PatentNo. 145,421, 1921), wherein an auxiliary screen grid was added whichsubstantially reduced the miller capacitance between the primary controlgrid and the anode. In summary, the addition of an additional controlelectrode resulted in the creation of a compound device that had thefunctional features of a cascode circuit arrangement of two triodedevices.

Moving forward to the semiconductor era, multiple gate arrangements 5were proposed for Field Effect devices, as shown in FIG. 2, to solve asimilar set of problems (U.S. Pat. No. 3,803,461). These prior art FETdevices were later utilized in a number of novel RF circuit topologies7, as shown in FIG. 3 (U.S. Pat. No. 4,167,681). Recently, as shown inFIG. 4, a novel discrete power HEMT FET device 9, utilizing anintegrated cascode structure 10, has been disclosed to improve theperformance of solid-state RF power amplifiers (U.S. Pat. No.7,126,426).

More specifically, in the case of vertically oriented field effectdevices, the utilization of multiple gate electrodes have been proposedfor a large number of purposes. For example, FIG. 5 illustrates a priorart vertical fin device 15 which utilizes multiple gates to control acommon primary channel structure (U.S. Pat. No. 7,126,426). Oneapplication of such a gate arrangement is to facilitate theimplementation of multiple-threshold logic circuits for digitalcomputing applications. This is a substantially different application ofmultiple gate electrode structures than the device of the presentinvention.

A more pertinent example of a vertical prior art device is shown in FIG.6 (U.S. Pat. No. 7,105,934). Prior art FinFET device 16, preferablyfabricated on a Silicon-On-Insulator (SOI) starting substrate, utilizesmultiple gates connected as a common node to control primary andsecondary channel structures, and thereby has reduced extrinsic deviceseries resistance. In the case of the device of FIG. 6, the utilizationof a single gate node is advantageous for realizing digital circuitfunctions, the efficiency of which can be substantially limited byinterconnect density considerations. In the case of analog andmixed-signal functions however, where interconnect densityconsiderations are typically more relaxed, the co-modulation ofdiffering adjoined channel structures may introduce non-linearity,thereby reducing the effectiveness of the device.

In spite of the improvements that have been discussed in the area ofmultiple-gate MOS Field Effect devices, a number of problems remain tobe solved, particularly in the domain of CMOS analog and mixed-signalcircuit applications. The device of the present invention addresses andsolves a number of additional problems in the art.

SUMMARY OF THE INVENTION

Accordingly, it is one object of the present invention to provide animproved, castellated-gate MOSFET tetrode device capable of fullydepleted operation.

It is another object of the present invention to provide such a devicehaving drive current per unit area increases up to an order-of-magnitudeor greater (>10×) than existing planar VLSI I/O devices.

Still another object of the present invention is to provide a high speedintegrated vertical I/O device having a tunable input or outputimpedance through the use of one or more additional gate terminals.

Yet another object of the present invention is to provide a castellatedgate MOSFET tetrode device capable of symmetrical operation with respectto the source and drain terminals.

Yet another object of the present invention is to provide a castellatedgate MOSFET device with one or two shielding gates, thereby providingimproved clock feedthrough immunity when the device is used as an analogsampling switch.

Still another object of the present invention is to provide acastellated-gate MOSFET tetrode device with reduced junction capacitanceas compared to its planer counterpart for the same drive current.

A still further object of the present invention is to provide acastellated-gate MOSFET tetrode device which has a physical designlayout and operational physical structure which is independent of thestarting wafer type, that is bulk, SOI, epi, strained-surface, orotherwise engineered.

A still further object of the present invention is to provide acastellated-gate MOSFET tetrode device which has a physical designlayout and operational physical structure which is substantiallycompatible with prior art castellated-gate MOSFET triode devicefabrication sequences.

To achieve the foregoing and other objects and in accordance with thepurposes of the present invention, as embodied and broadly describedherein, a castellated-gate MOSFET tetrode device capable of fullydepleted operation is disclosed. The device includes a semiconductorsubstrate region having an upper portion with a top surface and a lowerportion with a bottom surface. A source region and a drain region areformed in the semiconductor substrate region, and a channel-formingregion is also disposed therein between the source and drain regions.Trench isolation insulator islands, having upper and lower surfaces,surround the source and drain regions as well as the channel-formingregion. The primary channel-forming region includes a plurality of thin,spaced, vertically-orientated conductive channel elements that spanlongitudinally along the device between the source and drain regions. Afirst gate structure is provided in the form of a plurality of spaced,castellated first gate elements interposed between the primary channelelements, and a first top gate member interconnects the first gateelements at their upper vertical ends to cover the primary channelelements. A first dielectric layer separates the primary conductivechannel elements from the first gate structure. Either one or twoSecondary channel forming regions are created in a predetermined mannerlongitudinally along the vertically-oriented conductive channel elementsbetween the primary channel forming regions and the source and/or drainregions. One or two second gate structures are then provided in the formof additional pluralities of spaced, castellated second gate elementsinterposed between the secondary channel elements. A second top gatemember interconnects the second gate elements at their upper verticalends to cover the secondary channel elements. Finally, one or two seconddielectric layers separate the secondary conductive channel elementsfrom the second gate structure, thereby forming an integrated cascodedevice structure.

In one modification, the device further includes at least oneelectrically insulating material layer formed in the semiconductorregion lower portion beneath the source and drain regions. In one formof this modification, the electrically insulating material layer isspaced below the bottom surface of the trench isolation islands to forma common semiconductor connection in the lower portion of the device. Inaddition, the electrically insulating material layer may selectivelyabut the bottom surface of the shallow trench isolation islands and thechannel-forming regions.

In another modification of the invention, the source and drain regionsof the device are preferably of dual-polarity, each being a composite ofn-type and p-type dopant impurities.

In one further modification of the invention, the source and drainregions are each dually doped to create their dual polarity. In thisform, the dopant of the primary channel-forming region is of a firstconductivity type, the dopant of the upper portions of the source anddrain regions is of a second conductivity type at a degenerateconcentration, and the dopant of the lower portions of the source anddrain regions is of the first conductivity type but of an order ofmagnitude greater than the dopant level of the primary channel-formingregion.

In yet another alternate form of the invention, the dopant of theprimary channel-forming region is of a first conductivity type. Thedopant of the secondary channel-forming region may be of either a firstor second conductivity type, differing polarities, and at dopantconcentrations, up to degenerate levels, that may be set in apredetermined manner.

Another modification of the invention includes a castellated-gate MOSFETtetrode device which is capable of fully depleted operation and issubstantially independent of starting wafer type. The device includes asemiconductor substrate region of a first conductivity type, having anupper portion with a top surface and a lower portion with a bottomsurface. A dual-polarity source region is provided and has an upperhighly doped portion of a second conductivity type and a lower highlydoped portion of said first conductivity type but of a higherconcentration level than that of said substrate region. Likewise, adual-polarity drain region is also provided having an upper highly dopedportion of a second conductivity type and a lower highly doped portionof said first conductivity type but of a higher concentration level thanthat of said substrate region. A channel-forming region is deposedbetween the source and drain regions, the primary channel-forming regionincluding a plurality of thin, spaced, vertically-oriented conductivechannel elements that span longitudinally along the device between thesource and drain regions. Either one or two Secondary channel formingregions are created in a predetermined manner longitudinally along thevertically-oriented conductive channel elements between either ends ofthe primary channel forming regions, and the source and/or drainregions. Trench isolation insulator islands surround the dual-polaritysource and drain regions as well as the channel-forming regions, andhaving upper and lower surfaces. A first gate structure is provided inthe form of a plurality of spaced, castellated conductive first gateelements interposed longitudinally between and outside of the primarychannel elements, and a first top gate member interconnecting the firstgate elements at their upper vertical ends to cover the primary channelelements. A first dielectric layer serves to separate the primaryconductive channel elements from the first gate structure. Furthermore,one or two second gate structures are then provided in the form ofadditional pluralities of spaced, castellated second gate elementsinterposed between the secondary channel elements. A second top gatemember interconnects the second gate elements at their upper verticalends to cover the secondary channel elements. To complete the integratedcascode device structure, a second dielectric layer separates thesecondary conductive channel elements from the second gate structure.Finally, both first and second gate elements have a depth less than thelower surface of the shallow trench isolation islands.

Yet another modification of the invention includes a castellated-gateMOSFET tetrode device which is capable of fully depleted operation andis substantially independent of starting wafer type. The device includesa semiconductor substrate region of a first conductivity type, having anupper portion with a top surface and a lower portion with a bottomsurface. A single-polarity source region is provided, which is a highlydoped structure of a second conductivity type. Likewise, asingle-polarity drain region is provided, also being a highly dopedstructure of a second conductivity type. A channel-forming region isdeposed between the source and drain regions, the primarychannel-forming region including a plurality of thin, spaced,vertically-oriented conductive channel elements that span longitudinallyalong the device between the source and drain regions. Either one or twoSecondary channel forming regions are created in a predetermined mannerlongitudinally along the vertically-oriented conductive channel elementsbetween either ends of the primary channel forming regions, and thesource and/or drain regions. Trench isolation insulator islands surroundthe single-polarity source and drain regions as well as thechannel-forming regions, and having upper and lower surfaces. A firstgate structure is provided in the form of a plurality of spaced,castellated conductive first gate elements interposed longitudinallybetween and outside of the primary channel elements, and a first topgate member interconnecting the first gate elements at their uppervertical ends to cover the primary channel elements. A first dielectriclayer separates the primary conductive channel elements from the firstgate structure. In addition, one or two second gate structures are thenprovided in the form of additional pluralities of spaced, castellatedsecond gate elements interposed between the secondary channel elements.A second top gate member interconnects the second gate elements at theirupper vertical ends to cover the secondary channel elements. Completingthe integrated cascode device structure, a second dielectric layerseparates the secondary conductive channel elements from the second gatestructure. Finally, both first and second gate elements have a depthgreater than the lower surface of the shallow trench isolation islands.

An additional aspect of the invention includes a method of manufacturinga castellated-gate MOSFET tetrode device. The initial steps of themethod are substantially the same as that of the referenced method forfabricating a Castellated-Gate MOSFET in a triode configuration, andconsists of the steps of preconditioning a starting semiconductorsubstrate, and then applying active layer pad nitride masks to formshallow trench isolation islands in the substrate. A plurality of thinsemiconductor channel elements are formed by etching a plurality ofspaced gate slots to a first predetermined depth into the substrate. Theslots are then filled with a dielectric material. An area of thedielectric material is then cleared out within the gate slots to form agate slot spacer, followed by the deposition of a first gate dielectric.The slot regions are also filled with a first conductive gate material,and they are subsequently connected together at their upper end surfaceswith a first top gate layer, thereby forming a primary channelstructure. At this point, the ungated portion of the channel elementsmay be implanted, or otherwise doped to a predetermined concentrationand/or conductivity type. Next, an optional second spacer structure isformed around the first gate stack. A source and a drain region are eachimplanted at opposite end portions of the spaced, channel elements, withthe previously formed second spacer structure serving to maskintermediate channel forming regions between either end of the primarychannel structure. A predetermined area of previously deposed andplanarized Interlevel Dielectric (ILD) is cleared out, in addition to aspecified vertical portion of the gate slot spacer structure, followedby the deposition of a second gate dielectric. Finally, the second groupof slot regions are filled with a second conductive gate material, andconnected together at their upper end surfaces with a second top gatelayer, thereby forming a secondary channel structure, and completing theintegrated cascode device.

A further modification of the invention includes a second method ofmanufacturing a castellated-gate MOSFET tetrode device. In the secondmethod, the formation of the second spacer is no longer required to formself-aligned source and drain regions. Instead, a derived mask layer isemployed in a processing step after the partially cleared gate slotregions have been filled with a first dielectric and a first conductivegate material. A composite gate structure is temporarily formed thatincorporates masking features of the first gate and second gate. Thefirst gate portion of the temporary composite gate defines the primarychannel structure, and the remaining portion is utilized as a dummy gatewith which to self-align the source and drain regions. After the sourceand drain structures have been fabricated, predefined areas adjacent tothe first gate are cleared of material that includes previously deposedInterlevel Dielectric (ILD), composite gate conductor, and a specifiedvertical portion of the gate slot spacer structure. Finally, the secondgroup of slot regions are filled with a second conductive gate material,and connected together at their upper end surfaces with a second topgate layer, thereby forming a secondary channel structure, andcompleting a second method with which to fabricate the integratedcascode device of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings which are incorporated in and form a part ofthe specification illustrate preferred embodiments of the presentinvention and, together with a description, serve to explain theprinciples of the invention. In the drawings:

FIG. 1 illustrates a perspective view of one sub-section of thecastellated gate tetrode device of the embodiment illustrated in FIGS. 9and 9A;

FIG. 2 illustrates a perspective view of a prior art planar field effectdevice which incorporates an integrated cascode structure;

FIG. 3 shows a prior art circuit diagram which utilizes dual-gate fieldeffect transistors to realize an RF mixer function;

FIG. 4 illustrates a crossectional view and an equivalent circuitdiagram of a prior art integrated cascode discrete field effecttransistor device;

FIG. 5 illustrates a crossectional view of a prior art FinFET verticalfield effect transistor structure, wherein multiple separated gatescontrol a common first channel region;

FIG. 6 illustrates a perspective view of a prior art FinFET verticalfield effect transistor structure wherein multiple gate electrodeelements, connected as a common node, control first and second channelregions;

FIG. 7 illustrates a perspective view of one sub-section of thecastellated gate tetrode device of the embodiment illustrated in FIGS. 9and 9A;

FIG. 8 illustrates three equivalent circuit symbols for the castellatedgate tetrode device of the present invention, each representing adistinct embodiment;

FIG. 9 is a top view of the photolithography masking elements of a firstembodiment of the present invention, illustrating two similarorientations and one orientation 90° relative to the first twoorientations to illustrate the complete structure of the embodiment;

FIG. 9A is a cross-sectional view taken substantially along line 9A-9A′of FIG. 9;

FIG. 10 is a top view diagram of the common photolithography maskingelements of second, third, and fourth embodiments of the presentinvention, illustrating two similar orientations and one orientation 90°relative to the first two orientations to illustrate the completestructure of the embodiment;

FIG. 10A is a cross-sectional view taken substantially along line10A-10A′ of FIG. 10;

FIG. 10B is a cross-sectional view taken substantially along line10A-10A′ of FIG. 10;

FIG. 10C is a cross-sectional view taken substantially along line10A-10A′ of FIG. 10;

FIG. 11 is a generic flow diagram illustrating one basic process forfabricating a prior art castellated MOSFET triode device;

FIG. 12 is a generic flow diagram illustrating one basic process forfabricating a castellated gate tetrode device in accordance with thepresent invention, including the new flow's relationship to the priorart flow of FIG. 11;

FIG. 13 is a top view of a process step for patterning and etching afirst gate stack using a first gate mask in the same embodiment of thepresent invention initially presented in FIG. 9, illustrating twosimilar orientations and one orientation 90° relative to the first twoorientations to illustrate the complete structure of this step in makingthe embodiment;

FIG. 13A is a cross-sectional view taken substantially along line13A-13A′ of FIG. 13;

FIG. 14 is a top view of another subsequent process step for forming aspacer, as well as source and drain regions, through the application ofsource and drain masks in the same embodiment of the present invention,illustrating two similar orientations and one orientation 90° relativeto the first two orientations, to illustrate the complete structure ofthis step in making the embodiment;

FIG. 14A is a cross-sectional view taken substantially along line14A-14A′ of FIG. 14;

FIG. 15 is a top view of yet another subsequent process step forpatterning and etching vias with which to form a second gate using asecond gate mask in the same embodiment of the present invention,illustrating two similar orientations and one orientation 90° relativeto the first two orientations, to illustrate the complete structure ofthis step in making the embodiment;

FIG. 15A is a cross-sectional view taken substantially along line15A-15A′ of FIG. 15;

FIG. 16 is a generic flow diagram illustrating as second basic processfor fabricating a castellated gate tetrode device in accordance with thepresent invention, including the new flow's relationship to the priorart flow of FIG. 11;

FIG. 17 is a top view of a subsequent process step for using a derivedmask layer which incorporates both the first and second mask shapes inorder to form a composite gate stack, in the second embodiment of thepresent invention illustrating two similar orientations and oneorientation 90° relative to the first two orientations to illustrate thecomplete structure of this step in making the embodiment;

FIG. 17A is a cross-sectional view taken substantially along line17A-17A′ of FIG. 17;

FIG. 18 is a top view of a subsequent process step for applying a secondgate mask with which to remove the dummy portion of the composite gatestack by utilizing a multi-step anisotropic etch sequence, in the secondembodiment of the present invention, illustrating two similarorientations and one orientation 90° relative to the first twoorientations to illustrate the complete structure of this step in makingthe embodiment;

FIG. 18A is a cross-sectional view taken substantially along line18A-18A′ of FIG. 19;

FIG. 19 is a top view of the photolithography masking elements of thesecond embodiment of the present invention, illustrating two similarorientations and one orientation 90° relative to the first twoorientations to illustrate the complete structure of the embodiment; and

FIG. 19A is a cross-sectional view taken substantially along line19A-19A′ of FIG. 19, illustrating the completed form of the secondembodiment of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

In the field of castellated gate MOSFET devices, one attractive approachto the aforementioned problems in the area of analog and mixed-signalapplications is to incorporate one or two additional gate structures soas to form an integrated cascode device. FIG. 7 illustrates inperspective view a subsection of an improved version 240 of thecastellated gate MOSFET triode device 3 illustrated in FIG. 1. Theimproved castellated gate MOSFET tetrode 240 is capable of fullydepleted operation, and has a first top gate electrode 32, as well assecond top gate electrodes 115 which are separated from the first by adielectric layer. First and second gate structures control primary andsecondary channel structures (not shown), thus forming a compounddevice. As was the case of the prior art triode device 3, the improveddevice 240 of the present invention may incorporate dual-polarity sourceand drain structures consisting of self-aligned upper portions 58 andlower portions 62.

The terminal characteristics of the MOSFET tetrode device of the presentinvention can be inferred from the equivalent circuit symbols shown inFIG. 8. In it's simplest embodiment, castellated gate MOSFET tetrodedevice 18 incorporates a second gate electrode (G2 _(d)) on the drainside only, thus shielding the drain node (D) from the first gate (G1),and thereby reducing the Miller Capacitance when the device is utilizedin a common source amplifier configuration. Castellated gate MOSFETtetrode device 17 incorporates second gate electrodes at both the drainand the source sides which are joined together as a common second gatenode (G2). This symmetrical arrangement is useful when the device isutilized as an analog switch. Finally, castellated gate MOSFET tetrodedevice 18 incorporates independent second gate electrodes at both thedrain (G2 _(d)) and the source sides (G2 _(s)), thereby providing themaximum flexibility of control.

In its preferred embodiment, the composite DC electrical behavior of thecastellated-gate MOSFET tetrode device is dominated by the behavior ofthe primary channel structure. Consequently, the drive currentimprovement of the castellated-gate tetrode device over it's planarcounterpart follows from the referenced prior art triodecastellated-gate MOSFET, as described in the following equation

$\left. P_{drv} \middle| {}_{TG}{\cong {\beta {\frac{n\left( {{2z} + d} \right)}{{nd} + {\left( {n + 1} \right)W_{g}}} \cdot \left( \frac{\left. L_{\min} \right|_{PSG}}{\left. L_{\min} \right|_{TG}} \right)}}} \right.$

where Wg is the width of the primary gate slots, d is the gate slotspacing (channel thickness), and L_(eSG) and L_(eTG) are the minimumchannel lengths of a planer single-gate MOSFET and a tri-gated MOSFET,respectively. β represents the ratio of the multiple-gated andsingle-gated effective mobilities for the primary channel, and at agiven threshold voltage, where 0.75<β<1.00.

In the case of small-signal/AC behavior, the creation of a performanceimprovement metric for the castellated-gate tetrode, such as theprevious equation, is a more complex undertaking as it depends on thedesign parameters of the secondary channel structure(s). Referring backto the case of the castellated gate tetrode device 18 in FIG. 8, if thesecondary channel conductivity type and dopant levels are the same asthe primary channel, the equivalent circuit can be reduced to a cascodeconsisting of a primary castellated-gate MOSFET triode, havingnegligible extrinsic resistive component (R_(ext1)), in series with asecondary castellated-gate MOSFET triode, also having negligibleextrinsic resistive component (R_(ext2)), but with higher overlapcapacitance (C_(ov)) to the output node. The secondary castellated-gateMOSFET triode normally operates under constant bias in this situation,and acts to shield the output node from the drain node of the primarycastellated-gate device, thereby suppressing the Miller Effect withrespect to primary device when the MOSFET tetrode is utilized in acommon source amplifier configuration. Just as in the case of vacuumtube technology, the castellated gate MOSFET tetrode will exhibit alarger gain-bandwidth product (GBW) than an equivalently designedcastellated gate MOSFET triode.

With the general characteristics of the castellated gate MOSFET tetrodedevice introduced, a more detailed and specific embodiment of the deviceof the present invention will be described. Referring now to FIGS. 9 and9A, a version of the invention is illustrated having a “tri-gated”primary channel, along with its photo masking layers in one possibleembodiment using a low-doped bulk silicon substrate as the startingmaterial. FIG. 9 illustrates one device in two similar orientations andthen in an orientation 90° relative to the first two orientations toillustrate the complete structure from a top view as well as incross-section as illustrated by FIG. 9A. The device 240 includes asilicon substrate wafer 21 and a plurality of thin, adjoined siliconchannels 22,23 that span the distance between a source 24 and a drain26. Just as in the case of the prior art castellated MOSFET triode, theprimary channels 22 are formed by etching gate slots 28 into the activesilicon, filling the slots with a dielectric material, preferably oxide,clearing out an area of the dielectric material within the gate slots toform a spacer 114, deposing a first gate dielectric 84, and then fillingthe slot regions with a first conductive gate material to form aplurality of vertical, spaced first gate elements 30 which are connectedtogether by a first top gate 32. Subsequently, a secondary plurality ofgates are patterned after the formation of the source and drainstructures 24,26. This is achieved by applying a masking layer 53 whichoverlaps the gate slot masks 48 in the direction of channel length,thereby removing the remaining portion of the spacer structure 114.Next, a second gate dielectric 85 is deposed over the secondary channelelements 23. The device structure is completed by deposing and etchingback a second conducting material to form the second plurality of gates111, along with a second top gate 115. As shown in FIG. 9A, the primaryand secondary silicon channels 22,23 are preferably contiguous with thesemiconductor material of the original starting wafer 21 from which theywere fabricated. As such, they are continuously connected to thestarting wafer both electrically and thermally.

The source/drain structure 24, 26 of the device 240 is preferably acomposite of both N-Type and P-Type impurities, that is, they are ofdual-polarity. The depth and thickness of the source and drain implantlayers 24, 26 and their relation to the depth of the gate slots 28 arealso key parameters for the proper operation of the device. In theexample of FIGS. 9 and 9A, and in the case of a device of NMOS polarity,the upper portions 58, 60, respectively, of the source and drain regions24, 26 are degenerately doped n-type. This forms an actual p-n junctionto the body of the NMOS version of device 240, and an electricalconnection to the adjoined channels 22,23 of the device. The lowerportions 62, 64, respectively, of the source and drain regions 24, 26are heavily doped p-type in the NMOS version, such that the peak of thedoping profile is roughly coincident with the bottom gate oxide 116.This arrangement forms a channel stop by raising the device thresholdnear the bottom of the gate electrode, and greatly reduces a source ofelectrons with which to form an inversion layer at the lower surface ofthe bottom gate structure 116.

FIGS. 10 and 10A illustrate a second device embodiment 250 of thedisclosed device invention using a starting substrate 78 which has adielectric layer 77 in a lower portion. A Silicon-On-Insulator (SOI)wafer would be an example of such a starting substrate, and can beproduced using a variety of methods. Note that the device mask layoutremains substantially the same as the case of the device 240 with thebulk starting wafer 21 shown in FIGS. 9-9A. Substantially similar to thebulk silicon substrate device 240, the device 250 includes a pluralityof adjoined primary and secondary silicon channel elements 22,23 thatspan the distance between a source region 24 and a drain region 26.These primary and secondary channels are controlled by first and secondpluralities of gate elements 30,111, respectively, which are separatedfrom the channels using first and second gate dielectrics, 84,85.

As shown in FIG. 10A, the dielectric layer 77 of device embodiment 250is spaced below the bottom surfaces of the Shallow Trench Isolationislands 54,56. In another embodiment 252, shown in FIG. 10B, the devicecan be fabricated such that the bottom surfaces of the Shallow TrenchIsolation islands 54,56 abut the dielectric layer. In general, there areadvantages to leaving a common silicon connection 81, thus enabling theuse of body contacts which can be employed to eliminate device snapbackproblems as well as provide a path of higher thermal conductivity withwhich to dissipate heat.

In yet another embodiment 260 of the device of the present invention,the secondary channel elements 23′ have the same dopant concentration asthe source and drain regions 24,26 (see FIG. 10C). This is accomplishedby simply aligning the source and drain regions to the outer edges ofthe primary channel 22 prior to the construction of the second gateelements 111. In this configuration, the secondary channels 23′ functionas gated resistors, with the second gate structure 111,115 providingshielding between the primary gate and the source and/or drain nodes24,26.

At this point, it should be clear that the device described in theforegoing discussion may be constructed using a variety of materialtypes and methods. For example, the starting substrate 21 of FIG. 9A maybe selected from a group that includes, but is not limited to, bulk,epitaxial, or bonded silicon wafers. The substrates may additionallyinclude engineered substrates containing strained silicon layers and/orsilicon-germanium heterostructures as well as material systems otherthan silicon, including Silicon Carbide (SIC), Gallium Nitride (GaN),Gallium Arsenide (GaAs), and Indium Phosphide (InP), which structurallymay be epitaxial, bonded, or otherwise engineered. In addition, thesubstrates may incorporate predefined regions of differing materialtypes within which the device of the present invention is deposed. Thesepredefined regions may be specified by a physical design lithographymask which is substantially incorporated with the physical design masksof the disclosed device. Alternately, the predefined regions may exist apriori, and the device of the disclosed invention is simply aligned anddeposed within those regions using methods known in the art.

Similarly, the deposed components of the device of the present inventioncan also be selected from a wide variety of material types. For example,in the silicon realization of the device described in FIGS. 9-9A, thefirst gate dielectric 84 is preferably composed of silicon dioxide(SiO₂), however other oxides or dielectrics may also be used includinglanthanum oxide, hafnium oxide, oxynitride (ONO), or silicon nitride(Si₃N₄). Likewise, the deposed first and second gate conductors maypreferably be composed of n-type insitu-doped polysilicon, howevermid-gap metal gates such as tungsten, titanium, tantalum or compositesthereof, could also be used with appropriate changes to processingconductions.

An additional aspect of the present invention is the method with whichthe castellated gate MOSFET tetrode is fabricated. Now that thestructural characteristics of the device of the present invention havebeen thoroughly described, a more detailed and specific description offabrication methods will now be provided.

Method 1

As a reference, FIG. 11 illustrates a generic process flow 500 forfabricating a prior art castellated gate MOSFET triode which sharessimilar structural characteristics with the device of the presentinvention. Now referring to FIG. 12, a generic process flow 610 isillustrated which can be used to fabricate a castellated gate MOSFETtetrode device in accordance with the present invention, such as thefirst embodiment 240, and further derivative embodiments, 250,252,260.More generally, it should be understood that the processing stepsdisclosed herein are adaptable to any device covered by the claims ofthe present invention.

As shown in FIG. 12, the initial steps 612 of the fabrication sequence610 are substantially the same as the first four steps of fabricationsequence 500 used to construct a prior art castellated gate MOSFETtriode device. In summary, these initial steps include the selection ofa starting substrate 21, preprocessing steps associated with definingdoping profiles and levels, formation of dielectric filled channeldefining slots that reside within predefined active areas, and finallythe removal of a predefined portion of the dielectric spacer 114 to apredefined depth having a bottom oxide 116, thereby forming the primarychannel of the integrated cascode device of the present invention.Following the completion of these initial steps, the fabricationsequence proceeds to a set of steps by which the first gate is deposedand patterned.

Proceeding to the Gate 1 formation step 614 of the fabrication sequence,a first gate dielectric 84 is formed, preferably of silicon dioxide(SiO2) or oxynitride (ONO), although other dielectrics may also be used.These include but are not limited to hafnium oxide, lanthanum oxide, orsilicon nitride (Si3N4). The deposed first gate dielectric layer 84 inthe preferred embodiment will have a thickness (Tox) in the range of 50to 350 angstroms in order to support operating voltages (Vdd) in therange of 1.8 to 5.0 volts. After the formation of the first gatedielectric 84, a gate stack is disposed consisting of a gate conductor,an oxide (preferably BPTEOS) 154 which will serve as an etch stop, and asilicon nitride (Si3N4) cap 152. The silicon nitride film 152 hassignificant ion-implant stopping power as the result of its highermaterial density. This feature is required in order to perform theself-aligned source/drain implants without counter-doping non-metal gatematerials or the device channel itself. It should be noted that othergate-stack structures compatible with the preferred embodiment arepossible, including the formation of a polycide on a polysilicon gateconductor prior to the application of the nitride cap layer.

With the gate stack in place, the next step in the fabrication sequence610 for the preferred embodiment is to pattern a photoresist layer, withthe possible inclusion of the previously referenced anti-reflectivecoating, using the first gate mask 50, illustrated in FIG. 13. Athree-step etch sequence is preferably performed beginning with thesilicon nitride cap 152, followed by the oxide layer 154, and thenfinally the gate conductor. This procedure may be performed on amulti-chamber etch tool such as the Applied Materials Centura etchplatform. The resulting structure, minus the photoresist which is wellknown to the art, is shown in FIG. 13A.

In the next step of the fabrication sequence, a spacer is formed 616around the top first gate 32 in order to facilitate the creation of oneor two secondary channels 23. In general, this procedure involvesdeposing a dielectric, preferably oxide, in a uniform layer over thewafer, and then etching back the deposed material, leaving the spacerstructures around features that protrude from the surface of the wafer,one of which is the first top gate. Alternate approaches can also betaken, including combining the spacer procedure 616 and the source/drainformation procedure 618, as will be seen next.

With the cap nitride layer 152 still in place, a spacer 119 andself-aligned source and drain junctions 24, 26 will be formed in acombined sequence through the application of the source and drain masks46, as depicted in FIGS. 14-14A. Following the deposition andplanarization of a deposed dielectric, photoresist 190 is applied andpatterned using the source/drain masks 46. As discussed previously, thesource and drain structures 24, 26 of the device of the presentinvention preferably include, respectively, upper portions 58, 60 andlower portions 62, 64. In the case of an N-type device 20, thedopant-peak of the lower portions 62, 64 would be at approximately thesame depth as the bottom gate oxide 116, discussed previously withrespect to the trench formation process steps. In the case of an NMOSMOSFET tetrode, the lower portions 62, 64 of the source and drainimplants 24, 26 are preferably of the p+ conductivity type and can beformed using boron in the form of B11 or B12. The upper portions 58, 60of the source and drain junctions 24, 26 are preferably of an n+conductivity type for an NMOS MOSFET tetrode device, and are preferablyformed using phosphorous (P), arsenic (As), or other donor implantspecies individually or in combination. After the source and drainstructures have been fabricated, additional processing may be performed,including the optional removal of the capping nitride layer 152 in abath of hot phosphoric acid or other appropriate agent.

The application of the spacer 119 in the third procedure 616 of thefabrication sequence serves to self-align the source and drain regionsat a predetermined distance laterally from the primary channels 22,thereby facilitating the definition of the secondary channels 23. Asdepicted in FIGS. 15-15A, following the fabrication of the source anddrain structures, another interlevel dielectric layer (ILD), preferablyoxide, is deposed and polished-back, preferably usingChemical-Mechanical-Polishing (CMP). At this point, second gate masks 53(see FIG. 15) are used to pattern photoresist, and a multi-step etchprocedure is used to clear out predefined areas 114′ and 117 fromregions that include ILD 69, top first gate spacer 119, and gate slotspacer 114. Finally, as shown in FIG. 15B, a second gate dielectric 85is deposed, followed by a second gate conductor material 156. The secondgate conductor material is then polished back to form the second topgate 115, as well as pluralities of second gate elements 111.

Contact formation and wiring steps are now performed in the usual mannerknown in the art to create circuitry, with the resulting final structureillustrated in FIGS. 9 and 9A. It should be noted at this point that ifa SOI wafer is used as a starting substrate, the same process stepssummarized in FIG. 12, along with masking layers shown in FIG. 9 (andrepeated in FIG. 10), are used to create the structure illustrated inFIGS. 10A and 10B. Similarly, the fabrication sequence of FIG. 12 can beused with the spacer formation in procedure 616 omitted to produce theembodiment 260 of FIG. 10C. In this embodiment, the secondary channelsof the integrated cascode have been replaced with gated resistors 23′.

Method 2

Other embodiments of the device constructed in accordance with thepresent invention can be produced using a second fabrication sequence.In this sequence, a procedure is incorporated whereby a composite gatestructure is formed consisting of the first gate, as well as a remainingportion which acts as a dummy gate with which to self-align thesource/drain structures to the secondary channel(s). This second methodis summarized in FIG. 16, and will now be described.

Just as in the case of the first method 610, the initial steps 712 ofthe second fabrication sequence 710 (see FIG. 16) are substantially thesame as the first four steps of fabrication sequence 500 (FIG. 15) usedto construct a prior art castellated gate MOSFET triode device. Movingforward to the next procedure 714 in FIG. 16, the first gate dielectric84, preferably oxide, is deposed over the primary channel 22 in much thesame way as the first method 610. Also, as in 614, a gate stack isdisposed consisting of an n-type insitu-doped polysilicon conductor, anoxide (preferably BPTEOS) 154 which will serve as an etch stop, and asilicon nitride (Si3N4) cap 152. At this point in the procedure 714, thesecond fabrication sequence diverges, as will be seen next.

With the gate stack in place, the next step in the composite gateformation procedure 714 is to apply a derived mask layer 160 (see FIG.17); which includes the features from first gate 50 and second gate 53masks. Using a technique illustrated previously in FIG. 13A, amulti-step anisotropic etch procedure is now executed, yielding theresult of FIG. 17A. As shown in FIG. 17A, a composite gate structure hasbeen produced which consists of the first gate elements 30, a dielectriclayer 84 surrounding the primary channels 22, and a remainder 32′ whichwill serve as a hard mask with which to self-align the source/drainstructures in the following procedure.

The presence of the composite gate structure now makes the spacerformation procedure 716 an unnecessary sequence for defining thesecondary channel, and therefore it can be omitted. Referring back toFIG. 16, a subsequent procedure 718 will be used to form self-alignedsource and drain regions in the same manner as depicted in FIGS. 14-14Aof the first method 610. With the formation of the source and drainstructures completed, the capping nitride layer 152 may be optionallyremoved in a bath of hot phosphoric acid or other appropriate agent. Inthe final step of the procedure 718, an ILD layer, preferably oxide, isdeposed and planarized.

Referring now to FIGS. 18-18A, the final key steps 720 of the secondfabrication sequence begin with the patterning of photoresist 190 usingthe second gate mask 53. Next, a multi-step etch process is applied toclear out areas 117 and 114′ from regions that include the ILD 69, theremaining dummy gate stack material 32′, and the gate slot spacer 114.Finally, the procedure 720 to construct the second gate is completed bydeposing a second gate dielectric 85, followed by a second gateconductor material (preferably tungsten), and polishing back the secondconductor material using CMP. The end product of these steps is theformation of the second top gate 115, as well as pluralities of secondgate elements 111. As seen earlier in the first fabrication sequence(Method 1), contact and wiring structures can now be formed in the usualmanner known in the art to create circuitry, with the resulting finalstructure illustrated in FIGS. 19 and 19A.

The foregoing description and the illustrative embodiments of thisinvention have been described in detail in varying modifications andalternate embodiments. It should be understood, however, that theforegoing description of the present invention is exemplary only, andthat the scope of the present invention is to be limited to the claimsas interpreted in view of the prior art. Moreover, the inventionillustratively disclosed herein suitably may be practiced in the absenceof any element which is not specifically disclosed herein.

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 9. A method of manufacturing acastellated-gate MOSFET tetrode device comprising the steps of:pre-conditioning a starting semiconductor substrate; applying activelayer pad nitride masks to form trench isolation islands in saidsubstrate; forming a plurality of channel elements by etching aplurality of spaced gate slots to a first predetermined depth into saidsubstrate; filling said slots with a dielectric material; clearing out apredetermined area of said dielectric material within said gate slots toform a primary channel, a gate slot spacer and a bottom gate; depositinga first gate dielectric; filling said slot regions with a firstconductive gate material and connecting them together at their upper endsurfaces with a first top gate layer; implanting source and drainregions at opposite end portions of said spaced, channel elements, andhaving a predetermined separating distance along said elements from saidprimary channel to form one or two secondary channels; deposing aplanarized interlevel dielectric layer having a top surface; clearingout one or two predetermined regions adjacent to said first top gate,including a portion of said gate slot spacer; depositing a second gatedielectric; filling in said adjacent regions with a second conductivegate material to form a second gate structure; and planarizing saidsecond conductive material to be coincident with said top surface ofsaid interlevel dielectric layer.
 10. A method of manufacturing acastellated-gate MOSFET tetrode device comprising the steps of:pre-conditioning a starting semiconductor substrate; applying activelayer pad nitride masks to form trench isolation islands in saidsubstrate; forming a plurality of channel elements by etching aplurality of spaced gate slots to a first predetermined depth into saidsubstrate; filling said slots with a dielectric material; clearing out apredetermined area of said dielectric material within said gate slots toform a primary channel, a gate slot spacer and a bottom gate; depositinga first gate dielectric; forming a composite gate structure by fillingsaid slot regions with a first conductive gate material and connectingthem together at their upper end surfaces with a composite top gateelectrode; implanting source and drain regions at opposite end portionsof said spaced, channel elements, and having a predetermined separatingdistance along said elements from said primary channel to form one ortwo secondary channels; deposing a planarized interlevel dielectriclayer having a top surface; defining a first top gate structure byremoving one or two predefined portions of said composite top gateelectrode; clearing out one or two predetermined regions adjacent tosaid first top gate electrode, including a portion of said gate slotspacer; depositing a second gate dielectric; filling in said adjacentregions with a second conductive gate material to form a second gatestructure; and planarizing said second conductive material to becoincident with said top surface of said interlevel dielectric layer.11. The method as claimed in claim 10, wherein said startingsemiconductor substrate comprises a silicon-on-insulator wafer, andwherein said spaced gate slots are etched to the same depth as saidshallow trench isolation islands and all the way to said buriedinsulator layer.